Technical Field
The present invention relates to an integrated electronic device having a test architecture and to the test method thereof.
Description of the Related Art
As is known, as the complexity of integrated electronic devices increases and the number of data access pins increases, the desirability of tools enabling fast testing thereof, without having to contact all the pins one by one, increases. This has led, in the mid eighties, to devising a standard, initially called JETAG (Joint European Test Action Group) and subsequently called JTAG (Joint Test Action Group), which developed in 1990 into the IEEE 1149.1 standard, also referred to as TAP (Test Access Port) or also as BSA (Boundary Scan Architecture).
The above standard envisages addition of a test logic stage that is integrated in the electronic circuit (which is, in general, a digital circuit or a mixed digital-analog circuit) in order to:                test the interconnections between integrated circuits once they are assembled on a printed-circuit board or on some other substrate;        test the interconnections of the integrated circuit; and        monitor or modify the activities of the integrated circuit during its normal operation.        
According to this approach, the test logic stage (also referred to as Test Access Port—TAP) comprises a plurality of test cells or test registers, one for each pin of the device, which are connected to each other in cascade, a logic stage, and one or more further data registers, as shown in FIG. 1. Here, an integrated device 100, of a generic digital type, comprises an operating portion 102 and the test access port (TAP) 103 and has data access pins 110, which include both data input pins and data output pins. In turn, the test access port (TAP) 103 comprises a test logic circuitry 104 (see also FIG. 2), a boundary scan register 106 and a plurality of data registers 105 (see also FIG. 2), whereof only one is shown in FIG. 1. The boundary scan register 106 is generally arranged, in the layout of the integrated devices 100, in a boundary position with respect to the semiconductor chip so as to surround the operating portion 102 and simplify connection between the test cells 108 and the data access pins 110 of the integrated devices 100. The boundary scan register 106 is formed by the plurality of test cells 108, arranged according to a physical sequence determined by the position of the data access pins 110 around the operating portion and connected to each other in cascade according to the physical sequence via connection lines 130, formed using known integration techniques.
FIG. 2 shows a simplified diagram of the test logic circuitry 104 including a controller 112, an instruction register 113, an instruction-decoding register 114, and logic gates 115. The data registers 105 comprise, for example, a bypass register 120, a device-identification register 121, and one or more specific design registers 122, according to the choices of the designer of the integrated device 100. The sequential output bits of the data registers 105 and of the boundary scan register 106 are multiplexed through an output multiplexer 107, as well as through the logic gates 115, and are then outputted.
It is to be noted that the set formed by the data registers 105, the boundary scan register 106, and the output multiplexer 107 constitutes a register set 108 including data registers connected in parallel between a common serial input TDI (Test-Data Input) and a common serial output TDO (Test-Data Output). The instruction register 113 each time selects the data register (from the data registers 106, 120-122) that forms the activated serial path.
The access stage 103 is connected to the outside world and exchanges with it the following signals, supplied on purposely provided pins of the same name:
TCK—Test Clock: clock signal used by the test logic circuitry 104 and distinct from the system clock of the operating portion 102;
TMS—Test-Mode Select: signal that drives switching between the test mode and the operating mode;
TDI—Test-Data Input: test input data including both test instructions (for the test logic circuitry 104) and test data (for the register set 108), supplied on the corresponding test-data input pin TDI in serial mode;
TDO—Test-Data Output: test output data including the results of the tests supplied by the boundary scan register 106 and the data stored in the data registers 105, as well as the data of the instruction register 113 toward the corresponding test-data output pin TDO in serial mode;
TRST—Test Reset: optional, enables asynchronous reset of the TAP controller 112.
Each test cell 108 is coupled between a respective data access pin 110 and a respective input/output point 111 of the operating portion 102 of the integrated device 100 and is pre-arranged for overriding the functionality of the respective data access pin 110 in test mode. In practice, during normal operation of the integrated device 100, the test cells 108 are set so as not to affect the integrated device 100 and to enable passage of data and instructions between the operating portion 102 of the integrated device 100 and the data access pins 110. The test cells 108 are thus practically invisible. Instead, in the testing step, the test cells 108 are set so that an input bitstream at the test-data input pin TDI are passed from one test cell 108 to the next in the physical sequence, until all the test cells 108 have been loaded (loading of a test word). Then, the contents of the test cells 108 are supplied to the operating portion 102 of the integrated device 100 through the input/output points 111. Next, a result word obtained by processing the previous test word is loaded by the operating portion 102 of the integrated device 100 from the input/output points 111 into the output test cells 108. The bitstream of the result word is transferred sequentially from each test cell 108 to the next one on the entire sequence and sequentially from the last test cell 108, through the test logic circuitry 104, to the exterior, on the test-data output pin TDO.
FIG. 3 shows an embodiment of test cells 108 according to the above standard 1149.1. The test cells 108 are the same as each other, but are connected differently according to whether they are input test cells, designed to load the test word supplied from outside on the test-data input pin TDI, or output test cells, designed to receive the result word from the operating portion 102. In detail, each test cell 108 comprises four data terminals SI, SO, PI, PO, namely a test input SI, connected to a test cell 108 that precedes it in the physical sequence or to the test-data input pin TDI; a test output SO, connected to a test cell 108 that follows it in the physical sequence or to the multiplexer 107; a data input PI, connected to a data access pin 110 or to an input/output point 111 of the operating portion 102, according to whether the test cell is an input test cell or an output test cell, respectively; a data output PO, connected to an input/output point 111 of the operating portion 102 or to a data access pin 110, according to whether the test cell is an input test cell or an output test cell, respectively.
Furthermore, the test cell 108 has control inputs receiving control signals supplied by the test logic circuitry 104 including a mode signal Mode, which determines operation of the cell in test mode or in “transparent” mode with direct passage of the bits from the data input PI to the data output PO; a test-mode selection signal ShiftDR, which enables selective loading of the bit on the test input SI or the bit on the data input PI; a first clock signal ClockDR; and a second clock signal UpdateDR. The test cell 108 is substantially made up of two multiplexers 150, 151 with two inputs and two flip-flops 152, 153. In detail, a first multiplexer 150 receives the data SI and PI, is controlled by the test-mode selection signal ShiftDR, and has an output connected to the data input of the first flip-flop 152. The first flip-flop 152 receives the first clock signal ClockDR and has an output connected to the data input of the second flip-flop 153. The second flip-flop 153 receives the second clock signal UpdateDR and has an output connected to a first input of the second multiplexer 151. The second multiplexer 151 further receives the datum PI, is controlled by the mode signal Mode, and has an output connected to the data output PO.
In practice, the data input SI and the data output PO allow forming a sequence or chain of test cells, which may be loaded serially so that, at each pulse of clock TCK, the bits fed sequentially on the test-data input pin TDI are transferred from one test cell 108 to the next test cell 108 in the sequence, until all the test cells 108 are loaded. Then, the bits at the data outputs PO of the test cells 108 operating as input test cells are supplied in parallel to the operating portion 102. The system thus operates as a serial-to-parallel converter. At the end of the test by the operating portion 102, the test result (result word) is parallel supplied on the data inputs PI of the test cells 108 operating as output test cells. Then, the individual bits of all the test cells 108 are transferred sequentially (through the data outputs SO) towards the test-data output pin TDO; the system thus operates as a parallel-to-serial converter.
With the described architecture, unidirectional test cells 108 exist that always work either as input cells, co-operating with the other input test cells to transform the test words from the serial format, as supplied on the test-data input pin TDI, to the parallel format, as supplied to the operating portion 102 of the integrated device 100, or as output cells, co-operating with the other output test cells to transform the result word from the parallel format to the serial format as supplied to the test-data output pin TDO.
The sequence of the test cells 108 is not, however, determined by the implemented data transit direction but on the basis of other design criteria, typically taking into account the physical vicinity to the respective input/output point 111 of the operating portion 102 of the integrated device 100. See, for example, FIG. 4, which shows a particular case of input operating test cells (input test cells 108A) and output operating test cells (output test cells 108B) that alternate with each other.
It follows that, during loading of an input test word, supplied from outside, first all the test cells 108 are loaded, irrespective of whether they are input test cells or output test cells; likewise, during unloading of the processed word.
In practice, in the presence of M input test cells 108A and N output test cells 108B, in at least M+N clock pulses TCK all the test cells 108 are loaded with the test word and in as many clock pulses the result word is outputted. Thus, in the case of complex integrated devices 100, which have a large number of test cells 108, the operations of loading of the test word and unloading of the result word are rather long and burdensome, thus increasing the test time and thus the corresponding costs.
The aforementioned 1149.1 standard also envisages the possibility of testing a plurality of integrated devices 100, for example, mounted on a same printed-circuit board 140 (FIG. 5) and interconnected via interconnection paths 141. In this case, the various integrated devices 100 are cascaded via suitably designed test paths 142 that connect the respective boundary scan registers 106 in cascade. Furthermore, the test word is serially supplied on the test-data input pin TDI of a first integrated device 100 of the chain and is transferred from one integrated device 100 to the next one in the device chain, and the processed word is sequentially unloaded from the test-data output pin TDO of the last integrated device 100 in the chain.
In practice, to enable checking of the interconnection paths 141, the test word is loaded in sequence into all the test cells 108 of the boundary scan registers 106 of all the devices 100 through the test paths 142 and loaded in parallel through the data access pins 110. Instead, to enable checking of the operating portion 102 of each integrated device 100, the boundary scan registers 106 may operate as element for isolating each operating portion 102 from the signals supplied on the interconnection paths 141 during execution of a self-test.
The 1149.1 standard also envisages a test configuration for checking the interconnection paths 141 wherein the various devices 100 have independent and separate inputs TDI and outputs TDO.
Since checking each integrated device 100 may envisage sequential loading of all the test cells of the boundary scan registers 106, the test times are long. Furthermore, for testing the printed-circuit board, in the test operations the times involved are multiplied by the number of devices 100 contained in the board, with consequent disadvantageous lengthening of the test times.
The subject matter discussed in the Background section is not necessarily prior art and should not be assumed to be prior art merely as a result of its discussion in the Background section. Along these lines, any recognition of problems in the prior art discussed in Background section or associated with such subject matter should not be treated as prior art unless expressly stated to be prior art. Instead, the discussion of any subject matter in the Background section should be treated as part of the inventor's approach to the particular problem, which in and of itself may also be inventive.